Abstract
Processor-in-memory (PIM) architectures have been proposed in the recent years. One major objective of PIM is to reduce the performance gap between the CPU and memory. To exploit the potential benefits of PIM, we designed a statement-base parallelizing system ¡V SAGE(Statement-Analysis-Grouping-Evaluation) in [1][2][3]. From our pervious research, we find that the execution schedule is a critical factor to the performance of PIM systems. In this paper, we provide new scheduling mechanism for one-host and one-memory processors (1H-1M) and one-host and n-memory processors (1H-nM), respectively, to fully utilize all of the memory processors in PIM architectures. The experimental results of these two mechanisms are also discussed.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0613101-192127 |
| Date | 13 June 2001 |
| Creators | Jean, Hwa-Jyh |
| Contributors | Chih-Ping Chu, Shian-Shyong Tseng, Yeh-Ching Chung, Tsung-Chuan Huang, Nai-Wei Lin |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0613101-192127 |
| Rights | unrestricted, Copyright information available at source archive |
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