Return to search

Economic lot scheduling for multiple products on parallel processors

No description available.
Identiferoai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/25481
Date08 1900
CreatorsCarreno, Jose Juan
PublisherGeorgia Institute of Technology
Source SetsGeorgia Tech Electronic Thesis and Dissertation Archive
Detected LanguageEnglish
TypeDissertation
RightsAccess restricted to authorized Georgia Tech users only.

Page generated in 0.0019 seconds