This master’s thesis deals with the issue of digital to analog conversion and possibility of its realization in digital circuits. Goal of this project is to design sigma-delta digital to analog converter with resolution of 14 bits and frequency band (0 ÷ 20) kHz. Main functional blocks: interpolator and modulator sigma-delta will be realized like digital structures. Reconstruction filter will be realized like an analog structure. For design a check of parameters of designed converter programs MATLAB and Simulink are used. Designed digital structures will be described by VHDL language.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:219761 |
| Date | January 2012 |
| Creators | Soukup, Luděk |
| Contributors | Pristach, Marián, Fujcik, Lukáš |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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