n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs)
with copper electrodes prepared by a novel plasma etching process have been fabricated
and studied. Their characteristics are similar to those of TFTs with molybdenum
electrodes. The reliability was examined by extended high-temperature annealing and
gate-bias stress. High-performance CMOS-type a-Si:H TFTs can be fabricated with this
plasma etching method.
Electrical characteristics of a-Si:H TFTs after Co-60 irradiation and at different
experimental stages have been measured. The gamma-ray irradiation damaged bulk
films and interfaces and caused the shift of the transfer characteristics to the positive
voltage direction. The field effect mobility, on/off current ratio, and interface state
density of the TFTs were deteriorated by the irradiation process. Thermal annealing
almost restored the original state's characteristics.
Floating gate n-channel a-Si:H TFT nonvolatile memory device with a thin a-
Si:H layer embedded in the SiNx gate dielectric layer has been prepared and studied. The
hysteresis of the TFT's transfer characteristics has been used to demonstrate its memory function. A steady threshold voltage change between the "0" and "1" states and a large
charge retention time of > 3600 s with the "write" and "erase" gap of 0.5 V have been
detected. Charge storage is related to properties of the embedded a-Si:H layer and its
interfaces in the gate dielectric structure. Discharge efficiencies with various methods,
i.e., thermal annealing, negative gate bias, and light exposure, separately, were
investigated. The charge storage and discharge efficiency decrease with the increase of
the drain voltage under a dynamic operation condition. Optimum operating temperatures
are low temperature for storage and higher temperature for discharge.
a-Si:H metal insulator semiconductor (MIS) capacitor with a thin a-Si:H film
embedded in the silicon nitride gate dielectric stack has been characterized for memory
functions. The hysteresis of the capacitor's current-voltage and capacitance-voltage
curves showed strong charge trapping and detrapping phenomena. The 9 nm embedded
a-Si:H layer had a charge storage capacity six times that of the capacitor without the
embedded layer. The nonvolatile memory device has potential for low temperature
circuit applications.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/86004 |
| Date | 10 October 2008 |
| Creators | Nominanda, Helinda |
| Contributors | Kuo, Yue |
| Publisher | Texas A&M University |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Dissertation, text |
| Format | electronic, born digital |
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