Return to search

Metody částečné rekonfigurace programovatelných struktur / Partial reconfiguration methods based on programmable structures

This master's thesis dissertates of partial reconfiguration methods based on programmable structures. In theoretical part it deals with difference and modular-based method of Xilinx's FPGAs Partial reconfiguration. Options of both reconfiguration techniques were written for Spartan 3, Virtex II, Virtex 4 and Virtex 5 processors. Diference-based method was in practical part tested on Spartan 3E Starter Kit and modular-based on ML501 board. All configuration bitstreams are included on CD. Xilinx Inc. provided all needed software tools such as ISE9.2i and PlanAHEAD.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:217848
Date January 2009
CreatorsKolář, Jan
ContributorsKváš, Marek, Valach, Soběslav
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

Page generated in 0.0016 seconds