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Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits

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Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:ucin1268426324
Date05 August 2010
CreatorsPendela Venkata Ramanjuneya, Suryanarayana
PublisherUniversity of Cincinnati / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324
Rightsunrestricted, This thesis or dissertation is protected by copyright: some rights reserved. It is licensed for use under a Creative Commons license. Specific terms and permissions are available from this document's record in the OhioLINK ETD Center.

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