Although with VLSI technology advancement, system-on-chip integration will be the trend in the future. When chip design grows more complex, on chip IP modules communicate more frequently. Hence, on-chip communication bandwidth requirements increase dramatically. In order to satisfy such requirements, the investment of interconnection allocation, buffer memory, and associated control circuits affects overall communication performance as well as system cost considerably. In our research, we developed a computer-aided design synthesis method for SOC static communication problem. It includes combined evaluation of cost and performance of communication routing and scheduling, interconnection allocation, buffer memory and control design. It applies simulated annealing technique to compute perform-constrained near-optimal communication synthesis design. In the optimization process, we studied theoretical and software design of communication synthesis transformation and communication cost estimation.
It consists of several tasks:
l message scheduling transformation
l message routing transformation
l split and merge transformation of multiple-occurrence messages
l overall communication cost estimation
For a design generated from high level synthesis, this method will produce near-optimal communication synthesis results that satisfy required communication requirements.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0912103-153935 |
| Date | 12 September 2003 |
| Creators | Wu, Tsung-Han |
| Contributors | Chih-Chiang Cheng, Chia-Hsiung Kao, Tsung Lee |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0912103-153935 |
| Rights | unrestricted, Copyright information available at source archive |
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