The subject of master´s thesis the problematics of current loop. Within the thesis, the basic components of current loop and the possibilities of its usage are described. There has also been an analysis made of the crucial functions of analyzer which is currently being in the process of development. A focus is put on mode of source and measure. The related functions are crucial in terms of testing and simulation of current loop. Furthermore, the SPI is described and it is used to establish access to the analyzer’s display. The usage of FMEA method has been chosen for the purpose of circuit’s reliability assessment. Practical part describes development of the analyzer and its parts. FMEA method application for selected fault states is presented in final part.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:221310 |
| Date | January 2015 |
| Creators | Mládek, Ondřej |
| Contributors | B:TECH,, Petr Dobrovolný,, Kahle, Petr |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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