This master work of the main subject: Developing and analysis of peripheral serial interface microcontroller RISC8 that is similar to PIC 16C57, goes about all phases of developing microcircuits. There are analyzed ways of the developing system on chip, described hardware description languages. The first phase is to develop and model a code with one of HDL (hardware description languages) like a Verilog. For that reason are used such developing tools as Cadence LDV-5.1, that is used for compiling, elaborating and simulating of the design with graphical interface. The second phase - synthesis is done using products of Synopsys Company such a design analyzer. All phases presented in the manner like a sources, all processes, what have to be done, are described and shown with tables, pictures and other graphical tools. All results described in the same manner. All files presented electronically in compact disc, like source files, .log files, databases and other results. The last chapter of the work describes the result of synthesis in the manner of synthesis constructs comparing two languages: Verilog and SystemC.
| Identifer | oai:union.ndltd.org:LABT_ETD/oai:elaba.lt:LT-eLABa-0001:E.02~2005~D_20050524_183745-16346 |
| Date | 24 May 2005 |
| Creators | Dirsė, Žygimantas |
| Contributors | Jusas, Vacius, Lenkevičius, Antanas, Jokužis, Vytautas, Bareiša, Eduardas, Šeinauskas, Rimantas, Kazanavičius, Egidijus, Kaunas University of Technology |
| Publisher | Lithuanian Academic Libraries Network (LABT), Kaunas University of Technology |
| Source Sets | Lithuanian ETD submission system |
| Language | Lithuanian |
| Detected Language | English |
| Type | Master thesis |
| Format | application/pdf |
| Source | http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2005~D_20050524_183745-16346 |
| Rights | Unrestricted |
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