The development of neural networks has become one of the most interesting topics in the scientific community. Systems that are based on the brain behavior can find applications in a wide variety of fields, from simulating the brain to better understand it (applications in neuroscience), to control theory and super computing. Brain-like systems could possible be a new kind of computer architecture that will lead us away from the classic von Neumann architecture. That can help us bypass the problems that we now face, with the Moore’s low slowing down and complex problems becoming all the more common. With brain-like computing, we might be in the road to computer systems that are no longer programmed but taught. To-date, the most common platform for simulating such systems are the GPGPUs and super computers. But they lack on scalability, and real time simulations are far from trivial. Because of that there is an interest in custom hardware implementation of such system (in ASIC or FPGAs). In this work, we focus on the ASIC design of such a system. Specifically, with the characterization and design space exploration of the eBrain architecture, a hardware architecture for the BCPNN model. During the design process of an ASIC, in order to be able to characterize it, the simulation of the synthesized physical design of the RTL model is required. Those kinds of simulations require an extensive amount of time. In this thesis, to tackle with this problem a systemC model of the architecture is developed. This model is able to be modified and fits different configurations of a general hardware architecture. The systemC model can be used to reduce the amount of time the simulation requires and, by using back annotated data from synthesized parts of the hardware architecture, to provide us with accurate characterization of the design. In this work, we go through the basics of the BCPNN and the eBrain architecture. Then we develop a model that can emulate the behavior of the eBrain architecture in a probabilistic manner. A specific configuration is chosen to be explored. Furthermore, floating-point units are synthesized in the physical level in order to be able to back annotate their power measurements to the model. Moreover, the BCPNN equations are explored and implemented in an RTL level with the use of the floating-point units. Finally, an example configuration is simulated and its results are presented.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:kth-207028 |
| Date | January 2017 |
| Creators | Stathis, Dimitrios |
| Publisher | KTH, Skolan för informations- och kommunikationsteknik (ICT) |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | TRITA-ICT-EX ; 2017:8 |
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