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FPGA realization of low register systolic all one-polynomial multipliers over GF (2m) and their applications in trinomial multipliers

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Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:wright1465352514
Date08 June 2016
CreatorsChen, Pingxiuqi
PublisherWright State University / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=wright1465352514
Rightsunrestricted, This thesis or dissertation is protected by copyright: some rights reserved. It is licensed for use under a Creative Commons license. Specific terms and permissions are available from this document's record in the OhioLINK ETD Center.

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