The first topic of this thesis is to carry out a multi-symbol codec (encoder-decoder) design for interfacing variable-length and fixed-length data conversion of H.263. The poor memory efficient of the variable-length can be avoided while its advantages can be reserved. The proposed codec converts variable-length symbols to fixed-length packets which can be decoded parallelly. The basic idea is to encode extra symbols in the redundant bits of the fixed-length packets. This encoding scheme relaxes the intrinsic poor compression rate of the prior fixed-length data codec.
The second topic is a synthesizable Verilog code generator for the mentioned multi-symbol codec. According to different requirements and constraints of encoding bit rate, the generator can provide several different kinds of encoding modes by selecting proper parameters. Each codec generated by the generator is synthesizable by thorough simulations.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0711107-171127 |
| Date | 11 July 2007 |
| Creators | Lin, Jia-Hao |
| Contributors | Ing-Jer Huang, Sying-Jyan Wang, Chua-Chin Wang, Jih-Ching Chiu |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0711107-171127 |
| Rights | not_available, Copyright information available at source archive |
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