This dissertation presents a unique concept for a device architecture named the nanotube (NT) architecture, which is capable of higher drive current compared to the Gate-All-Around Nanowire architecture when applied to heterostructure Tunnel Field Effect Transistors. Through the use of inner/outer core-shell gates, heterostructure NT TFET leverages physically larger tunneling area thus achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. We discuss the physics of p-type (Silicon/Indium Arsenide) and n-type (Silicon/Germanium hetero-structure) based TFETs. Numerical TCAD simulations have shown that NT TFETs have 5x and 1.6 x higher normalized ION when compared to GAA NW TFET for p and n-type TFETs, respectively. This is due to the availability of larger tunneling junction cross sectional area, and lower Shockley-Reed-Hall recombination, while achieving sub 60 mV/dec performance for more
than 5 orders of magnitude of drain current, thus enabling scaling down of Vdd to 0.5 V.
This dissertation also introduces a novel thin-film-transistors architecture that is named the Wavy Channel (WC) architecture, which allows for extending device width by integrating vertical fin-like substrate corrugations giving rise to up to 50% larger device width, without occupying extra chip area. The novel architecture shows 2x higher output drive current per unit chip area when compared to conventional planar architecture. The current increase is attributed to both the extra device width and 50% enhancement in
field effect mobility due to electrostatic gating effects. Digital circuits are fabricated to demonstrate the potential of integrating WC TFT based circuits. WC inverters have shown 2× the peak-to-peak output voltage for the same input, and ~2× the operation frequency of the planar inverters for the same peak-to-peak output voltage. WC NAND circuits have shown 2× higher peak-to-peak output voltage, and 3× lower high-to-low propagation delay times when compared to their planar counterparts. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts. Finally, a WC based pass transistor logic multiplexer circuit is demonstrated, which has shown more than 5× faster high-to-low propagation delay compared to its planar counterpart at a similar peak-to-peak output voltage.
| Identifer | oai:union.ndltd.org:kaust.edu.sa/oai:repository.kaust.edu.sa:10754/621933 |
| Date | 11 1900 |
| Creators | Hanna, Amir |
| Contributors | Hussain, Muhammad Mustafa, Computer, Electrical and Mathematical Science and Engineering (CEMSE) Division, Ooi, Boon S., Schwingenschlögl, Udo, Banerjee, Sanjay K. |
| Source Sets | King Abdullah University of Science and Technology |
| Language | English |
| Detected Language | English |
| Type | Dissertation |
| Rights | 2017-12-06, At the time of archiving, the student author of this dissertation opted to temporarily restrict access to it. The full text of this dissertation became available to the public after the expiration of the embargo on 2017-12-06. |
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