Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation.
This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning.
A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation.:1 Introduction
1.1 The 3D Integration Approach for Electronic Circuits
1.2 Technologies for 3D Integrated Circuits
1.3 Design Approaches for 3D Integrated Circuits
2 State of the Art in Design Automation for 3D Integrated Circuits
2.1 Thermal Management
2.2 Partitioning and Floorplanning
2.3 Placement and Routing
2.4 Power and Clock Delivery
2.5 Design Challenges
3 Research Objectives
4 Planning Through-Silicon Via Islands for Block-Level Design Reuse
4.1 Problems for Design Reuse in 3D Integrated Circuits
4.2 Connecting Blocks Using Through-Silicon Via Islands
4.2.1 Problem Formulation and Methodology Overview
4.2.2 Net Clustering
4.2.3 Insertion of Through-Silicon Via Islands
4.2.4 Deadspace Insertion and Redistribution
4.3 Experimental Investigation
4.3.1 Wirelength Estimation
4.3.2 Configuration
4.3.3 Results and Discussion
4.4 Summary and Conclusions
5 Planning Through-Silicon Vias for Design Optimization
5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias
5.2 Multiobjective Design Optimization of 3D Integrated Circuits
5.2.1 Methodology Overview and Configuration
5.2.2 Techniques for Deadspace Optimization
5.2.3 Design-Quality Analysis
5.2.4 Planning Different Types of Through-Silicon Vias
5.3 Experimental Investigation
5.3.1 Configuration
5.3.2 Results and Discussion
5.4 Summary and Conclusions
6 3D Floorplanning for Structural Planning of Massive Interconnects
6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits
6.2 Corner Block List Extended for Block Alignment
6.2.1 Alignment Encoding
6.2.2 Layout Generation: Block Placement and Alignment
6.3 3D Floorplanning Methodology
6.3.1 Optimization Criteria and Phases and Related Cost Models
6.3.2 Fast Thermal Analysis
6.3.3 Layout Operations
6.3.4 Adaptive Optimization Schedule
6.4 Experimental Investigation
6.4.1 Configuration
6.4.2 Results and Discussion
6.5 Summary and Conclusions
7 Research Summary, Conclusions, and Outlook
Dissertation Theses
Notation
Glossary
Bibliography / Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück.
In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase.
Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich.:1 Introduction
1.1 The 3D Integration Approach for Electronic Circuits
1.2 Technologies for 3D Integrated Circuits
1.3 Design Approaches for 3D Integrated Circuits
2 State of the Art in Design Automation for 3D Integrated Circuits
2.1 Thermal Management
2.2 Partitioning and Floorplanning
2.3 Placement and Routing
2.4 Power and Clock Delivery
2.5 Design Challenges
3 Research Objectives
4 Planning Through-Silicon Via Islands for Block-Level Design Reuse
4.1 Problems for Design Reuse in 3D Integrated Circuits
4.2 Connecting Blocks Using Through-Silicon Via Islands
4.2.1 Problem Formulation and Methodology Overview
4.2.2 Net Clustering
4.2.3 Insertion of Through-Silicon Via Islands
4.2.4 Deadspace Insertion and Redistribution
4.3 Experimental Investigation
4.3.1 Wirelength Estimation
4.3.2 Configuration
4.3.3 Results and Discussion
4.4 Summary and Conclusions
5 Planning Through-Silicon Vias for Design Optimization
5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias
5.2 Multiobjective Design Optimization of 3D Integrated Circuits
5.2.1 Methodology Overview and Configuration
5.2.2 Techniques for Deadspace Optimization
5.2.3 Design-Quality Analysis
5.2.4 Planning Different Types of Through-Silicon Vias
5.3 Experimental Investigation
5.3.1 Configuration
5.3.2 Results and Discussion
5.4 Summary and Conclusions
6 3D Floorplanning for Structural Planning of Massive Interconnects
6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits
6.2 Corner Block List Extended for Block Alignment
6.2.1 Alignment Encoding
6.2.2 Layout Generation: Block Placement and Alignment
6.3 3D Floorplanning Methodology
6.3.1 Optimization Criteria and Phases and Related Cost Models
6.3.2 Fast Thermal Analysis
6.3.3 Layout Operations
6.3.4 Adaptive Optimization Schedule
6.4 Experimental Investigation
6.4.1 Configuration
6.4.2 Results and Discussion
6.5 Summary and Conclusions
7 Research Summary, Conclusions, and Outlook
Dissertation Theses
Notation
Glossary
Bibliography
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:28080 |
| Date | 14 March 2014 |
| Creators | Knechtel, Johann |
| Contributors | Lienig, Jens, Elst, Günter, Technische Universität Dresden |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | doc-type:doctoralThesis, info:eu-repo/semantics/doctoralThesis, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
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