Tracing represents that the information which are generated from the system can be collected for later observation and analysis. Because the SoC design becomes more and more complex, an advanced tracing is needed instead of processor tracing only. However, the generation rate and the size of real time system traces are so huge such that the compressor for tracing is needed. In this thesis, we purpose an on-chip bus trace analyzer for SoC¡¦s. This trace analyzer can allowed to perform accurate, successive trace collection in an unlimited time and can be used in various embedded system without influencing the operation of the bus system. The approach consists of two stages: (1) timing/signal abstraction stage and (2) trace reducing stage. And we show how to design and implement the on-chip bus trace analyzer. It can be also configured by users for different debugging uses. The experimental results show that this bus trace analyzer can reach a good compression ratio of 99% for AMBA system. Hence, by utilizing this trace analyzer, the support for debugging can be more powerful than existing method.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0906106-152058 |
| Date | 06 September 2006 |
| Creators | Lin, Chi-Hung |
| Contributors | Ko-Chi Kuo, Ing-Jer Huang, Jin-Hua Hong, Shu-Min Li |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906106-152058 |
| Rights | withheld, Copyright information available at source archive |
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