This thesis reports on a new implementation of high quality factor (Q) copper (Cu) inductors on CMOS-grade (10-20ohm.cm) silicon (Si) substrates using a fully CMOS-compatible process. A low-temperature (less than300C) fabrication sequence is employed to reduce the loss of Si wafers at RF frequencies by trenching the Si substrate. The high aspect-ratio (30:1) trenches are subsequently bridged over or refilled with a low-loss material to close the open areas and to create a rigid low-loss island (Trenched Si Island) on which the inductors can be fabricated. The method reported here does not require air suspension of the inductors, resulting in mechanically-robust structures that are compatible with any packaging technology. The metal loss of inductors is reduced by electroplating thick (~20m) Cu layer.
Fabricated inductors are characterized and modeled from S-parameter measurement. Measurement results are in good agreement with SONNET electromagnetic simulations. A one-turn 0.8nH Cu inductor fabricated on a Trenched Silicon Island (TSI) exhibits high Q of 71 at 8.75 GHz. Whereas, the identical inductor fabricated on a 20um thick silicon dioxide (SiO2) coated standard Si substrate has a maximum Q of 41 at 1.95GHz. Comparing the Q of inductors on TSI with that of other micromachined Si substrates reveals the significant effect of trenching the Si in reduction of the substrate loss. This thesis outlines the design, fabrication, characterization and modeling of spiral type Cu inductors on the TSIs.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/6991 |
| Date | 12 April 2005 |
| Creators | Raieszadeh, Mina |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Format | 3064545 bytes, application/pdf |
Page generated in 0.0021 seconds