The first topic of this thesis proposes a digital video decoder for NTSC. The new fully digital design employs a DDFS (digital direct frequency synthesizer) and an adaptive digital PLL to track and lock the demodulation carrier. The complexity of the digital video decoder, hence, is drastically reduced. The overall cost of the proposed design is 6.0 mm2 (39K gates). The maximum power dissipation is 86 mW at the hightest clock rate which is 21.48 MHz.
The second topic is to carry out a codec (encoder-decoder) design for interfacing variable-length and fixed-length data compression. The poor memory efficiency caused by the variable-length words converting into a fixed-length packet such that the compression can be hardwaredly and parallelly processing is significantly improved. The proposed codec is to encode more symbols in the redundant bits of the padding bits of the fixed-length packets. This novel encoding scheme relaxes the intrinsic poor bit rate of the traditional fixed-length data compression.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0812104-153002 |
| Date | 12 August 2004 |
| Creators | Chen, Chun-Chih |
| Contributors | chua-chin wang, Ing-Jer Huang, Jih-ching Chiu, Sying-Jyan Wang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812104-153002 |
| Rights | not_available, Copyright information available at source archive |
Page generated in 0.0018 seconds