This master's thesis dissertates of partial reconfiguration methods based on programmable structures. In theoretical part it deals with difference and modular-based method of Xilinx's FPGAs Partial reconfiguration. Options of both reconfiguration techniques were written for Spartan 3, Virtex II, Virtex 4 and Virtex 5 processors. Diference-based method was in practical part tested on Spartan 3E Starter Kit and modular-based on ML501 board. All configuration bitstreams are included on CD. Xilinx Inc. provided all needed software tools such as ISE9.2i and PlanAHEAD.
Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:217848 |
Date | January 2009 |
Creators | Kolář, Jan |
Contributors | Kváš, Marek, Valach, Soběslav |
Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
Source Sets | Czech ETDs |
Language | Czech |
Detected Language | English |
Type | info:eu-repo/semantics/masterThesis |
Rights | info:eu-repo/semantics/restrictedAccess |
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