This dissertation investigates the constraints which arise when switched-capacitor
(SC) delta-sigma modulators are designed for low-voltage operation, targeting also low
power dissipation, and proposes methods of improving the performance and optimizing
for low power dissipation. This is accomplished by identifying critical elements whose
performance can lead to increased power dissipation, as well as the fundamental
limitations of available analog circuit techniques. A prototype was designed and
fabricated, which reflected these findings, and therefore exhibited good performance and
nearly optimum power dissipation.
One of the key performance parameters is the dc gain of the amplifier in the first
stage; it should be high. This is necessary for high linearity and low quantization noise
leakage. In low-voltage operation, it may become impractical to use conventional
topologies employing cascoding techniques (e.g., folded-cascode) which provide high
gain in one single stage. Rather, cascaded structures have to be used. The disadvantage of
the latter is the necessity for frequency compensation which results in increased power
dissipation. Hence, another objective of this work is to exploit techniques which
compensate for the open-loop gain characteristic of the amplifier (dc gain and
nonlinearity), thus permitting the utilization of single-stage low-gain topologies.
Predictive correlated double sampling is one of such techniques and is analyzed in detail. / Graduation date: 1998
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/34151 |
| Date | 27 June 1997 |
| Creators | Grilo, Jorge |
| Contributors | Temes, Gabor C. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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