Return to search

VaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width

No description available.
Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:case1295638939
Date15 March 2011
CreatorsKunaparaju, Keerthi
PublisherCase Western Reserve University School of Graduate Studies / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=case1295638939
Rightsunrestricted, This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.

Page generated in 0.0017 seconds