"October 10th, 2001." / Errata included. / Bibliography: p. 179-185. / xii, 185 p. : ill. (some col.) ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / Looks at algorithms and architectures for implementing low-density parity-check codes to achieve reliable communication of digital data over an unreliable channel. Shows that published methods of finding LDPC codes do not result in good codes. Derives a cost metric for measuring short cycles in a graph due to an edge and proposes an algorithm for constructing codes through the minimisation of the cost metric. An encoding algorithm is derived by considering the parity check matrix as a set of linear simultaneous equations. A parallel architecture for implementing LDPC decoders is proposed and the advantages in terms of throughput and power reduction of this architecture are demonstrated through the implementation of 2 LSPC decoders in a 1.5V 0.16[mu]m CMOS process. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 2002
| Identifer | oai:union.ndltd.org:ADTP/263009 |
| Date | January 2001 |
| Creators | Howland, Chris (Christopher John) |
| Source Sets | Australiasian Digital Theses Program |
| Language | en_US |
| Detected Language | English |
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