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Developing Multi-Criteria Performance Estimation Tools for Systems-on-Chip

The work presented in this thesis targets the analysis and implementation of multi-criteria performance prediction methods for System-on-Chips (SoC).
These new SoC architectures offer the opportunity to integrate complete heterogeneous
systems into a single chip and can be used to design battery powered handhelds, security
critical systems, consumer electronics devices, etc. However, this variety in terms of application
usually comes with a lot of different performance objectives like power consumption,
yield, design cost, production cost, silicon area and many others. These performance requirements
are often very difficult to meet together so that SoC design usually relies on
making the right design choices and finding the best performance compromises.
In parallel with this architectural paradigm shift, new Very Deep Submicron (VDSM)
silicon processes have more and more impact on the performances and deeply modify the
way a VLSI system is designed even at the first stages of a design flow.
In such a context where many new technological and system related variables enter
the game, early exploration of the impact of design choices becomes crucial to estimate
the performance of the system to design and reduce its time-to-market.
In this context, this thesis presents:
- A study of state-of-the-art tools and methods used to estimate the performances of
VLSI systems and an original classification based on several features and concepts
that they use. Based on this comparison, we highlight their weaknesses and lacks to
identify new opportunities in performance prediction.
- The definition of new concepts to enable the automatic exploration of large design
spaces based on flexible performance criteria and degrees of freedom representing
design choices.
- The implementation of a couple of two new tools of our own:
- Nessie, a tool enabling hierarchical representation of an application along with
its platform and automatically performs the mapping and the estimation of
their performance.
-Yeti, a C++ library enabling the defintion and value estimation of closed-formed
expressions and table-based relations. It provides the user with input
and model sensitivity analysis capability, simulation scripting, run-time building
and automatic plotting of the results. Additionally, Yeti can work in standalone mode to provide the user with an independent framework for model estimation and analysis.
To demonstrate the use and interest of these tools, we provide in this thesis several
case studies whose results are discussed and compared with the literature.
Using Yeti, we successfully reproduced the results of a model estimating multi-core
computation power and extended them thanks to the representation flexibility of our tool.
We also built several models from the ground up to help the dimensioning of interconnect
links and clock frequency optimization.
Thanks to Nessie, we were able to reproduce the NoC power consumption results of
an H.264/AVC decoding application running on a multicore platform. These results were
then extended to the case of a 3D die stacked architecture and the performance benets
are then discussed.
We end up by highlighting the advantages of our technique and discuss future opportunities
for performance prediction tools to explore.

Identiferoai:union.ndltd.org:BICfB/oai:ulb.ac.be:ETDULB:ULBetd-03272009-115201
Date23 March 2009
CreatorsVander Biest, Alexis GJE
ContributorsVerkest Diederik, Le Moullec Yannick, Mathys Pierre, Robert Frédéric, Diguet Jean-Philippe, François Horlin, Milojevic Dragomir
PublisherUniversite Libre de Bruxelles
Source SetsBibliothèque interuniversitaire de la Communauté française de Belgique
LanguageEnglish
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://theses.ulb.ac.be/ETD-db/collection/available/ULBetd-03272009-115201/
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