No / This paper presents a novel and hardware-efficient architecture for power-of-two FFT processors. The proposed design is based on the phase-amplitude splitting technique which converts a DFT to cyclic convolutions and additions. The cyclic convolutions are implemented with a filter-like structure and the additions are computed with several stages of butterfly processing units. The proposed architecture requires no multiplier, and comparisons with other designs show it can save up to 39% total equivalent gates for an 8-bit 16-point FPGA-based FFT processor.
| Identifer | oai:union.ndltd.org:BRADFORD/oai:bradscholars.brad.ac.uk:10454/3129 |
| Date | January 2007 |
| Creators | Shepherd, Simon J., Noras, James M., Zhou, Yuan |
| Source Sets | Bradford Scholars |
| Language | English |
| Detected Language | English |
| Type | Article, No full-text in the repository |
Page generated in 0.0021 seconds