No / An area-efficient hardware architecture is used to map fully parallel cortical columns on Field Programmable Gate Arrays (FPGA) is presented in this paper. To demonstrate the concept of this work, the proposed architecture is shown at the system level and benchmarked with image and speech recognition applications. Due to the spatio-temporal nature of spiking neurons, this has allowed such architectures to map on FPGAs in which communication can be performed through the use of spikes and signal can be represented in binary form. The process and viability of designing and implementing the multiple recurrent neural reservoirs with a novel multiplier-less reconfigurable architectures is described.
| Identifer | oai:union.ndltd.org:BRADFORD/oai:bradscholars.brad.ac.uk:10454/9152 |
| Date | January 2015 |
| Creators | Ghani, A., See, Chan H., Migdadi, Hassan S.O., Asif, Rameez, Abd-Alhameed, Raed, Noras, James M. |
| Source Sets | Bradford Scholars |
| Detected Language | English |
| Type | Conference paper, No full-text in the repository |
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