Return to search

Computing with spikes, architecture, properties and implementation of emerging paradigms

In this thesis we study at a concrete practical level how computation with action potentials (spikes) can be performed. We address the problem of pro- gramming a dynamical system modeled as a neural network and considering both, hardware and software implementations. For this, we use a discrete- time spiking neuron model, which has been introduced in Soula et al. (2006), and called BMS in the sequel, whose dynamics is rather rich (see section 1.2.4). On one hand, we propose an efficient method to properly estimate the parameters (delayed synaptic weights) of a neural network from the observa- tion of its spiking dynamics. The idea is to avoid the underlying NP-complete problem (when both weights and inter-neural transmission delays are con- sidered in the parameters estimation). So far, our method defines a Linear Programming (LP) system to perform the parameters estimation. Another aspect considered in this part of the work is the fact that we include a reser- voir computing mechanism (hidden network), which permits us, as we show, to increase the computational power and to add robustness in the system. Furthermore these ideas are applied to implement input-output transforma- tions, with a method learning the implicit parameters of the corresponding transfer function. On the other hand we have worked on the development of numerical implementations permitting us to validate our algorithms. We also made contributions to code methods for spike trains statistics analysis and simu- lations of spiking neural networks. Thus, we co-develop a C++ library, called EnaS, which is distributed under the CeCILL-C free license. This library is also compatible with other simulators and could be used as a plugin. Finally we consider the emergent field of bio-inspired hardware im- plementations, where FPGA (Field Programmable Gate Array) and GPU (Graphic Processing Unit) technologies are studied. In this sense, we evalu- ate the hardware implementations of the proposed neuron models (gIF-type neuron models) under periodic and chaotic activity regimes. The FPGA- based implementation has been achieved using a precision analysis and its performance compared with that based on GPU.

Identiferoai:union.ndltd.org:CCSD/oai:tel.archives-ouvertes.fr:tel-00850264
Date24 January 2011
CreatorsRostro-Gonzalez, Horacio
PublisherUniversité Nice Sophia Antipolis
Source SetsCCSD theses-EN-ligne, France
LanguageEnglish
Detected LanguageEnglish
TypePhD thesis

Page generated in 0.0016 seconds