The first focus of this thesis is a basic scientific research in the field of super-regenerative receivers (SRRs) and, in particular, super-regenerative oscillators (SROs). In chapter 3, a theoretical analysis of SROs is performed and its nonlinear behavior is studied in both time and frequency domains. The cross-coupled architecture is studied as a special case, however, widely used topology in the SRO design. The start-up and decay envelopes of the oscillator output are studied in relation to the input. The SRO start-up time and the maximal achievable quenching frequency are investigated. For phase modulation purposes, the relation between the initial phases of the input and output signals is investigated. In addition, a frequency-domain analysis is performed to ease the characterization of test circuits at high frequencies where time-domain measurements are not possible. The analytical results are verified by circuit-level simulations and measurements of a 2.4-GHz SRO. This study provides design guidelines for the design of SROs and helps in determining the optimal system parameters when targeting both amplitude and phase
modulations.
The SRO concept and its phase sampling capability are further studied in chapter 4. For this purpose, two SRO circuits operating around 60GHz are investigated, designed − in both CMOS and SiGe BiCMOS technologies − and characterized. Different circuit techniques are studied in order to improve the energy efficiency and maximize the switching speed. For instance, a novel quenching technique to maximize the power efficiency is presented. This circuit approach includes a pulse generator, which generates the quench signal allowing to switch the SRO with a minimum duty cycle. In fact, the SRO input is sampled at the onset of oscillation and, therefore, it is unnecessary for the oscillator to run for a long time in its steady state. This allows to minimize the on-time of the SRO and to considerably reduce its power consumption. Compared to the state of the art, the circuit achieves by far the highest power efficiency of 21.7%. In addition, a novel switching scheme is presented in
order to maximize the quenching speed. This approach enables to greatly reduce the switching time constant, allowing to improve the SRO quench rate by approximately a factor of 3 compared to the state of the art. A record switching frequency of up to 10GHz is achieved.
The second focus of this thesis is the investigation of on-off-keying (OOK) receivers operating at a carrier frequency of 60GHz. OOK modulation schemes have the advantage of low circuit complexity and, therefore, low power consumption and small chip area. The drawback of low spectral efficiency can be mitigated by the large bandwidth at mm-wave frequencies, in particular, at the 60-GHz ISM band, 9GHz from 57 to 66GHz, which allows to achieve high data rates. The goals of this study are enhancing the speed, maximizing the energy efficiency and improving the sensitivity. For this purpose, several circuit approaches are studied. A highly efficient envelope detector and a novel limiting amplifier architecture with simultaneously large bandwidth and high gain ensure high-speed low-power operation. A high-gain low noise amplifier is employed to increase the sensitivity. A feedforward dc-offset cancellation technique is used to ensure the proper operation of the receiver. As a proof of concept, the chips are implemented in a 130-nm SiGe BiCMOS technology.
The OOK receiver achieves a record data rate of up to 20Gb/s at a bit-error-rate less than 10^(-12). The low power consumption and the ultra high speed capability allow a highly energy-efficient operation of only 2.2pJ/bit.
Finally, this thesis studies the design of 60-GHz amplifiers. In fact, one of the main challenges of transmitting data at mm-wave frequencies is the high free-space path loss, which limits the transmission range. To alleviate this issue, amplifiers with high output power at the transmitter side and with low noise figure and high gain at the receiver side are required. Chapter 6 investigates the design of a low noise amplifier (LNA), with the study focus being achieving simultaneously large bandwidth, high gain, low noise figure and low power consumption in order to enable a high-speed receiver with high power efficiency and high range. The LNA achieves a bandwidth of 23GHz, a gain of 23.8dB and an average noise figure of 3.2dB and consumes only 8mW, remarkably improving the state of the art. In addition, this chapter presents the investigation and design of a 60-GHz power amplifier with an output power of up to 14.7dBm and a small chip area to ensure a sufficient communication range at the transmitter side.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:93754 |
| Date | 26 September 2024 |
| Creators | Ferschischi, Ali |
| Contributors | Ellinger, Frank, Wang, Hua, Technische Universität Dresden |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, doc-type:doctoralThesis, info:eu-repo/semantics/doctoralThesis, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
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