Multi-threaded applications are needed to realize the full potential
of new chip-multi-threaded machines. Such applications are
very difficult to program and orchestrate correctly, and transactional
memory has been proposed as a way of alleviating some of the programming
difficulties. However, transactional memory can directly
be applied only to critical sections, while conditional synchronization
remains difficult to implement correctly and efficiently.
This dissertation describes EasySync, a simple and inexpensive extension
to transactional memory that allows arbitrary conditional
synchronization to be expressed in a simple and composable way.
Transactional memory eliminates the need to use locks and provides
composability for critical sections: atomicity of a transaction is
guaranteed regardless of how other code is written. EasySync provides
the same benefits for conditional synchronizations: it eliminates
the need to use conditional variables, and it guarantees wakeup
of the waiting transaction when the real condition it is waiting for
is satisfied, regardless of whether other code correctly signals that
change. EasySync also allows transactional memory systems to efficiently
provide lock-free and condition variable-free conditional
critical regions and even more advanced synchronization primitives,
such as guarded execution with arbitrary conditional or guard code.
Because EasySync informs the hardware the that a thread is
waiting, it allows simple and effective optimizations, such as stopping
the execution of a thread until there is a change in the condition
it is waiting for. Like transactional memory, EasySync is backward compatible
with existing code, which we confirm by running unmodified
Splash-2 applications linked with an EasySync-based synchronization
library. We also re-write some of the synchronization
in three Splash-2 applications, to take advantage of better code readability,
and to replace spin-waiting with its more efficient EasySync
equivalents.
Our experimental evaluation shows that EasySync successfully
eliminates processor activity while waiting, reducing the number of
executed instructions by 8.6% on average in a 16-processor CMP.
We also show that these savings increase with the number of processors,
and also for applications written for transactional memory
systems. Finally, EasySync imposes virtually no performance overheads,
and can in fact improve performance.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/10517 |
| Date | 10 April 2006 |
| Creators | Naik, Aniket Dilip |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Format | 729035 bytes, application/pdf |
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