The objective of this research is to present a low power modem technology for a high speed millimeter wave wireless system.
The first part of the research focuses on a robust ASIC design methodology. There are several aspects of the ASIC flow that require special attention such as logical synthesis, timing driven physical placement, Clock Tree Synthesis,
Static Timing Analysis, estimation and reduction of power consumption and LVS and DRC closure.
The latter part is dedicated to high speed baseband circuits such as Coherent and Non coherent demodulator which are critical components of a multi-gigabit wireless communication system. The demodulator operates at input data rates of multiple gigabits per second, which presents the challenge of designing the building blocks to operate at speeds of multiple GHz. The high speed complex multiplier is a major component of the non coherent demodulator. As part of the coherent demodulator the complex multiplier derotates the input sequence by multiplying with cosine and sine functions, Costas error calculator computes the phase error in the derotated input signal. The NCO (Numerically controlled Oscillator) is a look up table based system used to generate the cosine and sine functions, used by the derotator.The CIC filter is used to decimate the costas error signal as the loop bandwidth is significantly smaller compared to the sampling frequency. All these modules put together form the coherent demodulator which is an integral part of the wireless communication system. An implementation of Serdes is also presented which acts as an interface between the baseband modules and the RF front end.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/41084 |
| Date | 13 May 2010 |
| Creators | Muppalla, Ashwin K. |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Thesis |
Page generated in 0.002 seconds