Miniaturisation of electronic chips poses challenges at the design stage. The
progressively decreasing circuit dimensions result in complex electrical behaviour
that necessitates complex models.
Simulation of complex circuit models involves extraordinarily large compu-
tational complexity. Such complexity is better managed through Model Order
Reduction. Model order reduction has been successful in large reductions in
system order for most types of circuits, at high levels of accuracy. However,
multiport circuits with large number of inputs/outputs, pose an additional
computational challenge. A strategy based on
exible clustering of interconnects
results in more e cient reduction of multiport circuits. Clustering methods
traditionally use Krylov-subspace methods such as PRIMA for the actual model
reduction step. These clustering methods are unable to reduce the model order to
the optimum extent. SVD-based methods like Truncated Balanced Realization
have shown higher reduction potential than Krylov-subspace methods.
In this thesis, the di erences in reduction potential and computational cost
thereof between SVD-based methods and Krylov-subspace methods are identi ed,
analyzed and quanti ed. A novel algorithm has been developed, utilizing a
particular combination of both these methods to achieve better results. It
enhances the clustering method for model reduction using Truncated Balanced
Realization as a second-level reduction technique. The algorithm is tested and
signi cant gains are illustrated. The proposed novel algorithm preserves the
other advantages of the current clustering algorithm.
| Identifer | oai:union.ndltd.org:IISc/oai:etd.ncsi.iisc.ernet.in:2005/2774 |
| Date | January 2014 |
| Creators | Milind, R |
| Contributors | Raha, Soumyendu |
| Source Sets | India Institute of Science |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Relation | G26303 |
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