Chip temperature is increasing with continued technology scaling due to increased power density and decreased device feature sizes. Since temperature has significant impact on performance and reliability, accurate thermal and circuit analysis are of great importance. Due to the shrinking device feature size, effects occurring at the nanometre scale, such as ballistic transport of energy carriers and electron tunneling, have become increasingly important and must be considered. However, many existing thermal and circuit analysis methods are not able to consider these effects efficiently, if at all. This thesis presents methods for accurate and efficient multi-scale thermal and circuit analysis. For circuit analysis, the simulation of single-electron device circuits is specifically studied.
To target thermal analysis, in this work, ThermalScope, a multi-scale thermal analysis method for nanometre-scale IC design is developed. It unifies microscopic and macroscopic thermal physics modeling methods, i.e., the Boltzmann transport and Fourier modeling methods. Moreover, it supports adaptive multi-resolution modeling. Together, these ideas enable efficient and accurate characterization of nanometre-scale heat transport as well as chip-package level heat flow. ThermalScope is designed for full chip thermal analysis of billion-transistor nanometre-scale IC designs, with accuracy at the scale of individual devices. ThermalScope has been implemented in software and used for full chip thermal analysis and temperature-dependent leakage analysis of an IC design with more than 150 million transistors.
To target circuit analysis, in this work, SEMSIM, a multi-scale single-electron device simulator is developed with an adaptive simulation technique based on the Monte Carlo method. This technique significantly improves the time efficiency while maintaining accuracy for single-electron device and circuit simulation. It is shown that it is possible to reduce simulation time up to nearly 40 times and maintain an average propagation delay error of under 5% compared to a non-adaptive Monte Carlo method. This simulator has been used to handle large circuit benchmarks with more than 6000 junctions, showing efficiency comparable to SPICE, with much better accuracy. In addition, the simulator can characterize important secondary effects including cotunneling and Cooper pair tunneling, which are critical for device research. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-09-26 13:33:12.389
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OKQ.1974/1508 |
| Date | 27 September 2008 |
| Creators | Allec, NICHOLAS |
| Contributors | Queen's University (Kingston, Ont.). Theses (Queen's University (Kingston, Ont.)) |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Format | 2936149 bytes, application/pdf |
| Rights | This publication is made available by the authority of the copyright owner solely for the purpose of private study and research and may not be copied or reproduced except as permitted by the copyright laws without written authority from the copyright owner. |
| Relation | Canadian theses |
Page generated in 0.0191 seconds