The scaling of VLSI technology has allowed extensive integration of processing resources
on a single chip. Consequently, programmable chips is able to have a high logic and memory
capacity for implementation of complex systems. Field-programmable gate arrays (FPGAs) with their embedded memory and other specialized functionality have become viable
alternatives in many cases to costly application-specific integrated circuits as a system-on-chip (SoC) substrate. However, on-chip bus-based interconnects are no longer suitable for complex SoC design because of its limited scalability. The network-on-chip (NoC)paradigm has therefore emerged as a scalable approach for addressing this challenge.
FPGAs can also adopt the NoC paradigm in order to support more complex SoC implementations. The elements for NoC support can be implemented in conventional programmable logic within an FPGA, however, a dedicated approach for these NoC elements
can lead to better performance and more efficient utilization of on-chip FPGA resources. A fixed network topology can be a disadvantage in NoC platforms due to misalignment with application requirements. It is therefore desirable to incorporate a certain level of configurability even for embedded NoC support within an FPGA.
This thesis presents the design and implementation of a configurable router intended as a dedicated embedded module for NoC support in an FPGA. The goal is to provide a general NoC infrastructure for the FPGA platform that balances trade-offs with regard to logic complexity, resource utilization, and flexibility. The configurable router provides flexibility in implementing a variety of network topologies with the convenience of a 3-bit input to the router for configuration. All of the necessary routing functionality for each topology is implemented in logic for performance and area efficiency. The overall
router design provides general NoC support with reduced complexity, thereby achieving
area efficiency and an adequate clock frequency for typical operation in conjunction with embedded soft processors.
Synthesis results are presented at the router level in order to characterize the hardware overhead for implementations in programmable logic as well as standard-cell technology, and at the system-level in order to evaluate overall system resource utilization. Operational results are shown at router level to demonstrate correctness and at system level to demonstrate
functionality of the multiprocessor systems that utilizes the configurable router. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-09-24 23:24:01.907
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OKQ.1974/1516 |
| Date | 27 September 2008 |
| Creators | Pau, Ronny |
| Contributors | Queen's University (Kingston, Ont.). Theses (Queen's University (Kingston, Ont.)) |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Format | 2046266 bytes, application/pdf |
| Rights | This publication is made available by the authority of the copyright owner solely for the purpose of private study and research and may not be copied or reproduced except as permitted by the copyright laws without written authority from the copyright owner. |
| Relation | Canadian theses |
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