This thesis presents the design and analysis of two high speed analog laser driver stages (LDS) for use in a passive optical network (PON) upstream burst-mode transmitter (BM-Tx) using low cost complementary metal oxide semiconductors (CMOS) technology. The maturation of CMOS technology has lead to aggressive scaling of device sizes which has made it an increasingly attractive technology for high speed analog design. CMOS provides high levels of integration as it is the industry standard for digital circuits, analog and digital systems can share one substrate reducing costs. Additionally CMOS is a more cost effective solution than traditional expensive high speed analog substrates.
A 2.5 Gbps LDS fabricated in 0.18 um CMOS technology is presented. The LDS uses a two stage per-amplifier. Stage one consists of a cascode differential pair with a source follower voltage buffer, while stage two consists of a shunt inductively peaked differential pair using active inductors. A differential pair composed of large transistors is used in an open drain configuration for the output stage. Measurements of S-parameters are presented which accurately agree with simulations. Electrical eye diagram measurements are presented which demonstrate the LDS is able to provide a modulation current of 14.6-58 mA. 10%-90% approximate rise/fall times of 230/260 ps was obtained for a modulation current of 58 mA. Power consumption of the core was determined to be 68.5 mW, while the chip consumed an area of 0.8 mm x 0.7 mm including pads.
A 10 Gbps LDS fabricated in 0.18 um CMOS technology is also presented. The LDS uses a cascode differential pair for the output stage. The per-amplifier for this design consists of a differential pair and utilizes spiral inductors for series inductive peaking between the per-amplifier and output stage. Measurements of S-parameters are presented which accurately agree with simulations. Electrical eye diagram measurements are presented which demonstrate the LDS is able to provide a modulation current of 22.6-62 mA. 10%-90% rise/fall time of 87 ps and 75 ps are respectively obtained while operating at maximum modulation current. The core of the LDS consumes a power of 287 mW, while the chip consumed an area of 0.79 mm x 0.7mm.
The measured electrical eye diagrams for the 2.5 Gbps and the 10 Gbps meet the timing requirements for the GPON standard. Further work is needed to investigate whether or not the timing requirements would still be met once the CMOS chips are integrated with commercial laser diodes. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-09-24 10:43:33.418
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OKQ.1974/6078 |
| Date | 24 September 2010 |
| Creators | O'FARRELL, Michael |
| Contributors | Queen's University (Kingston, Ont.). Theses (Queen's University (Kingston, Ont.)) |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Rights | This publication is made available by the authority of the copyright owner solely for the purpose of private study and research and may not be copied or reproduced except as permitted by the copyright laws without written authority from the copyright owner. |
| Relation | Canadian theses |
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