Microprocessor systems have been advancing at a phenomenal rate, with each new generation introducing improved fabrication processes and architectural innovations. Unfortunately, traditional fabrication techniques cannot sustain this exponential growth indefinitely. Thus, additional research into conventional design methodologies, such as those involving asynchronous design techniques, is essential to maintain the current trend.
The primary objective of this research was to explore the viability of asynchronous design techniques as an alternative to current synchronous design methods. In order to simulate the design complexities involved in a real-world system, the MIPS-II R2000 pipelined microprocessor was selected as the basis for comparison. All of the experimental processors were designed in VHDL on an FPGA using the Altera Quartus II design package. The processors were tested using timing simulations with various benchmarks to determine the advantages and disadvantages of each design technique.
Four distinct asynchronous processors with varying handshaking and synchronization methods were designed and compared to the baseline synchronous processor. Although, in theory, each of the asynchronous design variations had its merits, it was clear that not all of them were well suited for practical use in a large-scale microprocessor environment. Three of the asynchronous processors suffered from an excessive amount of synchronization overhead that drastically reduced their overall system performance to the point where they performed considerably worse than the baseline synchronous processor. However, one asynchronous processor performed considerably better: with only a 1.5 percent increase in logic complexity, it outperformed the baseline synchronous processor by over 10 percent on a sorting test benchmark and had a maximum theoretical speedup of over 36 percent.
Therefore, it is evident that asynchronous designs have the potential to improve the performance of traditional synchronous systems. However, designing efficient and hazard-free asynchronous logic on an FPGA proved to be challenging and time-consuming. With additional research and further design tool improvements to facilitate the creation of optimized glitch-free logic, asynchronous design methodologies may become a viable alternative to traditional synchronous designs and contribute to the current trend of microprocessor advancement. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-12-19 01:30:22.248
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OKQ.1974/949 |
| Date | 20 December 2007 |
| Creators | Hoshino, Robert |
| Contributors | Queen's University (Kingston, Ont.). Theses (Queen's University (Kingston, Ont.)) |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Format | 5342713 bytes, application/pdf |
| Rights | This publication is made available by the authority of the copyright owner solely for the purpose of private study and research and may not be copied or reproduced except as permitted by the copyright laws without written authority from the copyright owner. |
| Relation | Canadian theses |
Page generated in 0.0024 seconds