This thesis introduces a new approach to compilation for FPGAs, which we call direct synthesis. We take a technology-mapped circuit netlist and directly map it into a pre-placed and routed FPGA overlay. Solving this problem may help to address the increasing portion of compile time that is attributed to placement and routing, and the tremendous amount of area and energy consumed by the highly flexible FPGA routing network. This thesis presents a direct synthesis algorithm and an algorithm for generating the pre-placed and routed FPGA overlays. Using the direct synthesis flow which we have designed, we can successfully map circuits less than 100 BLEs in size, after modest modi cations to the architecture of the FPGA overlay circuit. While we show that direct synthesis problem is challenging, further architectural modi cations are proposed which can allow the direct
synthesis of larger circuits to succeed.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/65549 |
| Date | 25 June 2014 |
| Creators | Di Matteo, Daniel |
| Contributors | Rose, Jonathan |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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