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Field Programmable Gate Arrays (FPGAs) have many modern applications. A feature of FPGAs is that they can be reconfigured to suit the computation. One such form of reconfiguration, called partial reconfiguration (PR), allows part of the chip to be altered. The smallest part that can be reconfigured is called a frame. To reconfigure a frame, a fixed number of configuration bits are input (typically from outside) to the frame.
Thus PR involves (a) selecting a subset C <font face=symbol>Í</font> S of k out of n frames to configure and (b) inputting the configuration bits for these k frames. The, recently proposed, MU-Decoder has made it possible to select the subset C quickly. This thesis involves mechanisms to input the configuration bits to the selected frames.
Specifically, we propose a class of architectures that, for any subset C <font face=symbol>Í</font> S (set of frames), constructs a path connecting only the k frames of C through which the configuration bits can be scanned in. We introduce a Basic Network that runs in <font face=symbol>Q</font> (k log n) time, where k is the number of frames selected out of the total number n of available frames; we assume the number of configuration bits per frame is constant. The Basic Network does not exploit any locality or other structure in the subset of frames selected. We show that for certain structures (such as frames that are relatively close to each other) the speed of reconfiguration can be improved. We introduce an addition to the Basic Network that suggests the fastest clock speed that can be employed for a given set of frames. This enhancement decreases configuration time to O(k log k) for certain cases. We then introduce a second enhancement, called shortcuts, that for certain cases reduces the time to an optimal O(k). All the proposed architectures require an optimal <font face=symbol>Q</font>(n) number of gates.
We implement our networks on the CAD tools and show that the theoretical predictions are a good reflection of the network<font face=symbol>¢</font>s performance.
Our work, although directed to FPGAs, may also apply to other applications; for example hardware testing and novel memory accesses.</body>
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| Identifer | oai:union.ndltd.org:LSU/oai:etd.lsu.edu:etd-04112016-050653 |
| Date | 05 May 2016 |
| Creators | Ashrafi, Arash |
| Contributors | Vaidyanathan, Ramachandran, Koppelman, David, Trahan, Jerry |
| Publisher | LSU |
| Source Sets | Louisiana State University |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lsu.edu/docs/available/etd-04112016-050653/ |
| Rights | unrestricted, I hereby certify that, if appropriate, I have obtained and attached herein a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to LSU or its agents the non-exclusive license to archive and make accessible, under the conditions specified below and in appropriate University policies, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. |
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