In this thesis, we present low latency general concatenated code structures
suitable for parallel processing. We propose parallel decodable serially concatenated
codes (PDSCCs) which is a general structure to construct many
variants of serially concatenated codes. Using this most general structure we
derive parallel decodable serially concatenated convolutional codes (PDSCCCs).
Convolutional product codes which are instances of PDSCCCs are
studied in detail. PDSCCCs have much less decoding latency and show almost
the same performance compared to classical serially concatenated convolutional
codes. Using the same idea, we propose parallel decodable turbo
codes (PDTCs) which represent a general structure to construct parallel concatenated
codes. PDTCs have much less latency compared to classical turbo
codes and they both achieve similar performance.
We extend the approach proposed for the construction of parallel decodable
concatenated codes to trellis coded modulation, turbo channel equalization,
and space time trellis codes and show that low latency systems can be
constructed using the same idea. Parallel decoding operation introduces new problems in implementation. One such problem is memory collision which occurs when multiple decoder units attempt accessing the same memory device. We propose novel interleaver structures which prevent the memory collision problem while achieving performance close to other interleavers.
| Identifer | oai:union.ndltd.org:METU/oai:etd.lib.metu.edu.tr:http://etd.lib.metu.edu.tr/upload/12608110/index.pdf |
| Date | 01 January 2007 |
| Creators | Gazi, Orhan |
| Contributors | Yilmaz, Ali Ozgur |
| Publisher | METU |
| Source Sets | Middle East Technical Univ. |
| Language | English |
| Detected Language | English |
| Type | Ph.D. Thesis |
| Format | text/pdf |
| Rights | To liberate the content for public access |
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