This thesis presents the development of CMOS readout electronics for microbolometer type infrared detector arrays. A low power output buffering architecture and a new bias correction digital-to-analog converter (DAC) structure for resistive microbolometer readouts is developed / and a 384x288 resistive microbolometer FPA readout for 35 µ / m pixel pitch is designed and fabricated in a standard 0.6 µ / m CMOS process. A 4-layer PCB is also prepared in order to form an imaging system together with the FPA after detector fabrication.
The low power output buffering architecture employs a new buffering scheme that reduces the capacitive load and hence, the power dissipation of the readout channels. Furthermore, a special type operational amplifier with digitally controllable output current capability is designed in order to use the power more efficiently. With the combination of these two methods, the power dissipation of the output buffering structure of a 384x288 microbolometer FPA with 35 µ / m pixel pitch operating at 50 fps with two output channels can be decreased to 8.96% of its initial value.
The new bias correction DAC structure is designed to overcome the power dissipation and noise problems of the previous designs at METU. The structure is composed of two resistive ladder DAC stages, which are capable of providing multiple outputs. This feature of the resistive ladders reduces the overall area and power dissipation of the structure and enables the implementation of a dedicated DAC for each readout channel. As a result, the need for the sampling operation required in the previous designs is eliminated. Elimination of sampling prevents the concentration of the noise into the baseband, and therefore, allows most of the noise to be filtered out by integration.
A 384x288 resistive microbolometer FPA readout with 35 & / #956 / m pixel pitch is designed and fabricated in a standard 0.6 & / #956 / m CMOS process. The fabricated chip occupies an area of 17.84 mm x 16.23 mm, and needs 32 pads for normal operation. The readout employs the low power output buffering architecture and the new bias correction DAC structure / therefore, it has significantly low power dissipation when compared to the previous designs at METU. A 4-layer imaging PCB is also designed for the FPA, and initial tests are performed with the same PCB. Results of the performed tests verify the proper operation of the readout. The rms output noise of the imaging system and the power dissipation of the readout when operating at a speed of 50 fps is measured as 1.76 mV and 236.9 mW, respectively.
| Identifer | oai:union.ndltd.org:METU/oai:etd.lib.metu.edu.tr:http://etd.lib.metu.edu.tr/upload/3/12610390/index.pdf |
| Date | 01 February 2009 |
| Creators | Toprak, Alperen |
| Contributors | Akin, Tayfun |
| Publisher | METU |
| Source Sets | Middle East Technical Univ. |
| Language | English |
| Detected Language | English |
| Type | M.S. Thesis |
| Format | text/pdf |
| Rights | To liberate the content for public access |
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