Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018. / This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. / Cataloged from student-submitted PDF version of thesis. / Includes bibliographical references (pages 143-149). / Autonomy is becoming an increasingly desirable feature for very small nano/pico robots to navigate cluttered and confined indoors environments such as collapsed buildings, caves, etc. Robot perception (i.e., semantic and geometric understanding) is considered the computation bottleneck in autonomous navigation systems because of the high dimensionality of the problem. For example, multi-scale object detection is desired for robustness, which requires significant data expansion. Additionally, a 3D map size grows overtime while the robot explores the environment, which requires computation power and large memory size. In this thesis, we introduce ASIC solutions that enable real-time and low power perception. First, the thesis demonstrates energy-efficient and high-throughput object detection accelerators for semantic understanding, which can process full HD (19201080, 60 fps) videos with energy consumption between 0.36 to 1.74 nJ/pixel. On-the-fly processing, parallel architectures, and image pre-processing are used to reduce the overhead of multi-scale detection using rigid-body models. Detection accuracy can be doubled with deformable parts models, but requires 35 more computation. To overcome this overhead, we exploit data compression, computation pruning, and basis projection for an overall 5 power reduction and 3.6 smaller memory size. Second, this thesis presents an algorithm and hardware co-design approach to enable real-time and energy-efficient localization and mapping for geometric understanding, using visual-inertial odometry. The chip (Navion) processes 752480 stereo frames at up to 171 fps, with an energy consumption between 1.6 to 3.5 nJ/pixel. Parallelism, rescheduling, resource sharing, exploiting sparsity, and image compression are applied to overcome the high dimensionality of the problem, resulting in 4.1 memory size reduction, and enabling full integration. Navion can adapt to different environments to maximize accuracy, throughput and energy-efficiency trade-offs. To the best of our knowledge, this thesis presents the first fully integrated VIO system in an ASIC. / by Amr Suleiman. / Ph. D.
| Identifer | oai:union.ndltd.org:MIT/oai:dspace.mit.edu:1721.1/117847 |
| Date | January 2018 |
| Creators | Suleiman, Amr S. (Amr AbdulZahir) |
| Contributors | Vivienne Sze., Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science., Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. |
| Publisher | Massachusetts Institute of Technology |
| Source Sets | M.I.T. Theses and Dissertation |
| Language | English |
| Detected Language | English |
| Type | Thesis |
| Format | 149 pages, application/pdf |
| Rights | MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission., http://dspace.mit.edu/handle/1721.1/7582 |
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