In this thesis, a simple on-chip automatic frequency tuning circuit is presented. The tuning circuit is improved from voltage-controlled filter (VCF) frequency tuning circuit. We use a single time constant (STC) circuit to substitute the voltage-controlled filter.
The STC circuit can produce a controllable delay time clock. The tuning circuit uses the constant delay time to tune the frequency of the filter. The design of a STC circuit is easy. Because the circuit is simple, the tuning circuit has less chip area and less power consumption.
The circuit has been fabricated with 0.35£gm CMOS technology. It operates with supply voltages ¡Ó1.5 V. The filter operates at a 3-dB frequency of 10MHz. In simulation, the frequency tuning circuit has a 3-dB frequency tuning error of less than 12% and the power consumption less than 9.05mW over a range of supply voltages (¡Ó10%), operating temperatures (-20¢J to 70¢J) and five models of SPICE model.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0118108-133444 |
| Date | 18 January 2008 |
| Creators | Chang, I-fan |
| Contributors | Ko-chi Kuo, Chia-hsiung Kao, Chua-chin Wang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0118108-133444 |
| Rights | not_available, Copyright information available at source archive |
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