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Hardware Implementation for Variable Length FFT Processor

¡@¡@A single chip of variable length FFT processor is presented in this thesis. This processor can be applied for the applications with 128/256/512/1024/2048-point FFT. This processor is based on SDF (single path delay feedback) pipeline architecture with radix-2^3 computation element. The number of bits for input data and twiddle factors is carefully selected by system simulation to meet the requirements of OFDM system. In addition, we propose a feedback twiddle factor generator to instead the lookup table for twiddle factors to reduce the storage size of memory.
The FFT processor is carried out by CMOS 0.35£gm 2P4M process with core area 3.381x3.3625 mm^2. In the gate level simulation, the output data rate of this FFT processor is above 22.72MHz, so the processor can meet the requirement of IEEE 802.16e standard.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0215107-012450
Date15 February 2007
CreatorsLiang, Wen-ko
ContributorsJu-ya Chen, none, none, none, none
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0215107-012450
Rightsnot_available, Copyright information available at source archive

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