In system-on-chips, system architecture designs greatly affect cost, performance,
and power consumption of the systems. In system design time, we thus need to
perform system architecture exploration. In order to effectively support architecture
exploration, we improve de-efficiency of current architecture description languages and
produce new ways of architecture description, including multiple architecture pattern
descriptions and generalized coding description. Together with existing architecture
description methods, we form a generalized architecture description language. In this
thesis research, in order to support verification of designs in the generalized architecture
description language, we designed its simulator software. The simulator should
support the descriptions of the architecture description language, including structural
description, behavioral description, coding description, multiple architecture pattern
descriptions, and hardware data structures. We implemented the simulator software in
several software modules, including simulator engine, parser design, interpreter design,
generalized decoder design, multiple architecture pattern descriptions, and hardware
data structures. We thus can effectively support the verification capability of the
architecture description language.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0221111-162645 |
| Date | 21 February 2011 |
| Creators | Luo, Ming |
| Contributors | none, none, Tsung Lee |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0221111-162645 |
| Rights | campus_withheld, Copyright information available at source archive |
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