In the System on a Chip () era, more components are embedded in one chip. Therefore, it has been an important issue to assist verification and debugging by observing the signals inside of a chip. The bus signals tracing is a general method to resolve it. However, the quantities of signals that have to be traced in an are very huge, we must to reduce the trace data as more as possible. Because of the reasons described as above, we propose a hardware called multi-resolution bus tracer to overcome these problems in this thesis. In the bus tracer, user can changes the observed accuracy of tracing signals dynamically during the program execution, and reduces all those signals efficiently. The experiment results show that bus tracer can achieve 85% average compressed ratio on the forward tracing, and 84% average compressed ratio on the backward tracing. In the other hand, the software called trace data analyzer not only transfers the trace signals into Value Change Dump (VCD) file format but also provides some essential analyses for user observation. Finally, our IP (Intelligent Property) has been integrated into a real platform: 3D Graphics Acceleration, and tape-out successfully. Therefore, using the multi-resolution bus trace analyzer can promote the abilities of system debugging efficiently.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0320108-162451 |
| Date | 20 March 2008 |
| Creators | Shiue, Wen-Chi |
| Contributors | Shiann-Rong Kuang, Kuen-Jong Lee, Ing-Jer Huang, Jih-ching Chiu |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0320108-162451 |
| Rights | not_available, Copyright information available at source archive |
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