In this thesis, we present an implementation of a low-power digital signal processor. We design the hardware units and analyze the instruction set for digital signal process applications. Besides, the power consumption issue is considered. We present two solutions to reduce the power consumption. We also discuss the test pattern generations to verify this DSP processor. Finally, the concept of IP design is considered in this design.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0623102-183014 |
| Date | 23 June 2002 |
| Creators | Fu, Szu-jui |
| Contributors | Shen-fu Hsiao, Yun-nan Chang, Shiann-rong Kuang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623102-183014 |
| Rights | not_available, Copyright information available at source archive |
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