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A CMOS SRAM Using Dynamic Threshold Voltage Wordline Transistors

This thesis includes two topics. The first topic is a CMOS SRAM using dynamic threshold voltage wordline-transistors, which is focused on high speed applications. The second one is a high voltage generator for FLASH memories. The generated high voltages are applied to the wordline controlled transistors during access and verification operations.
By taking advantage of the large current provided by low Vth and low leakage current provided by high Vth, a CMOS SRAM using dynamic threshold voltage wordline transistors is presented. The design of a 4-Kb SRAM is measured to possess a 2.2 ns access time, and consume 43.6 mW in the standby mode. The highest operating clock rate is estimated to be 667 MHz.
A high voltage generator using 4 clocks with two phases is presented to provide a high voltage supply required by FLASH memories during programming mode and erase mode operations. The circuit is implemented by TSMC 0.25um 1P5M CMOS process. It can provide as high as +11.7 V and -11.6 V by given VDD=2.5 V.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0623103-173734
Date23 June 2003
CreatorsChen, Tian-Hau
ContributorsShie-Jue Lee, Lon-Rong Hu, Chua-Chin Wang, Shen-Fu Hsiao
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623103-173734
Rightsnot_available, Copyright information available at source archive

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