In this paper, we present a low-power low-cost 6-bits, ADC using selective reference voltage technique. Using selective reference voltage technique, the different bit uses different comparator can be achieved. Meanwhile, the outputs from comparators are a binary code which can be used for generating logic condition thereby controlling the switches. Because the conventional n bits flash ADC requires 2n - 1 comparators and its power, area and input capacitance are all proportional to 2n - 1. Whereas, the proposed n bits ADC needs only n comparators which can save more power and area, and its input capacitance are proportional to n only, and keep high speed.
Our proposed ADC is design by TSMC 1P6M 0.18£gm process with 6-bits resolution, 1.8V power supply. The signal input range 0.5V~1.1V, sampling rate 256MS/s, DNL +0.46LSB~ -0.49LSB, INL +0.85LSB~ -0.05LSB. In addition, the FOM of the ADC is only 0.26 pJ/Conv and the power consumption is only 4.2mW.It is good for a low-power and low cost customer electronic application.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0705105-135326 |
| Date | 05 July 2005 |
| Creators | Shieh, Chung-Hsiao |
| Contributors | none, none, none, none, none |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705105-135326 |
| Rights | not_available, Copyright information available at source archive |
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