This thesis includes two topics. The first topic is an ADFS¡]All Digital Frequency Synthesizer¡^using a Flying Adder architecture. The second one is a low-power and low-latency 2-dimensional bypassing signed multiplier.
In the first topic, the ADFS is implemented by only using the standard cell library of TSMC¡]Taiwan Semiconductor Manufacturing Company¡^0.18 £gm 1P6M CMOS process. The turn-around time is effectively reduced. Furthermore, the portability and reusability of the proposed design is significantly enhanced. The design provides stable clock signals with fast switching time.
In the second topic, the proposed multiplier is carried out by Baugh-Wooley algorithm using 2-dimensional bypassing units. The proposed bypassing units automatically skip redundant signal transitions when either the horizontally¡]row¡^partial products or vertically¡]column¡^operands are zero.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0706109-133656 |
| Date | 06 July 2009 |
| Creators | Lu, Yu-cheng |
| Contributors | Sying-Jyan Wang, Chua-Chin Wang, Chih-Peng Li, Shu-Min Li |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-133656 |
| Rights | not_available, Copyright information available at source archive |
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