Continuous-time sigma-delta modulator can be applied to wireless communications, photography and MP3 player. Portable electronics products became mainstream the design of a low power consumption analog circuit become important. Therefore, this paper presents a low power consumption continuous-time sigma-delta modulator.
The low-power continuous-time sigma-delta modulator includes one-bit quantizer and a third-order loop filter consisting of resistor-capacitor integrators. Through the modified Z-transform, the discrete time loop filter design is transformed to the continuous time loop filter design.
The proposed sigma-delta modulator used TSMC 0.18£gm CMOS 1P6M standard process, and its supply voltage is 1V, oversampling ratio is 32, bandwidth is 200 KHz, effective number is 13bit, power consumption is 1.5mW.
Keywords: GSM, low power consumption, low power supply, continuous-time, sigma-delta modulator.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0712112-144604 |
| Date | 12 July 2012 |
| Creators | Liu, Jun-hong |
| Contributors | Jyi-Tsong Lin, Tzyy-Sheng Horng, Ko-Chi Kuo, Chia-Hsiung Kao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712112-144604 |
| Rights | user_define, Copyright information available at source archive |
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