In this proposal, an advanced local oscillator with high resolution, low phase noise and fast switching
characteristics is designed for wireless communication applications. The circuit is based on fractional-N
frequency synthesis technique in which the use of delta-sigma modulator can remove the fractional spurs
effectively. The mechanism in regard to fractional spurs and phase noise for a fractional-N frequency
synthesizer will be studied and simulated by developing proper mathematical models. In the
implementation of the local oscillator, the analog circuit includes a 1000-1033 MHz VCO, crystal
oscillator and loop filter. The digital circuit includes a phase frequency detector, dual modulus divider
and 3rd order delta-sigma modulator. At first a FPGA will be used to prototype the digital circuit.
The final digital circuit will be implemented in a CMOS process and require 3V operation with low
current consumption. The design specifications include that under 1 KHz resolution the phase noise
levels are less than -90 dBc/Hz at frequency offets within a loop bandwidth more than 100 KHz.
Spurious components are less than -90 dBc/Hz and switching time is less than 1 ms over a 30 MHz
tuning range.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0714100-222433 |
| Date | 14 July 2000 |
| Creators | Peng, Kang-Chun |
| Contributors | Hui-Ru Zhuang, Tzyy-Sheng Horng, Zong-Lin Wu, Cheng-Fu Chang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0714100-222433 |
| Rights | unrestricted, Copyright information available at source archive |
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