In this thesis, an FFT (Fast Fourier Transform) hardware circuit is designed for OFDM systems. A new memory table permutation deletion method, which can reduce the size of memory storing twiddle factors table, is proposed. The architecture of the FFT circuit is based on the faster split-radix algorithm with SDF (Single-path Delay Feedback) pipeline structure. The bits number of the signal is carefully selected by system simulation to meet the system requirements. Based on the simulation results, a small area FFT circuit is carried out for OFDM systems.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0720105-155609 |
| Date | 20 July 2005 |
| Creators | Tsai, Hung-Chieh |
| Contributors | Ju-Ya Chen, Jih-ching Chiu, Jieh-Chian Wu, none, Ken-Huang Lin |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0720105-155609 |
| Rights | not_available, Copyright information available at source archive |
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