Conventional logic circuit designs are based on fully complementary CMOS logic circuits. In the past decade, many Pass-Transistor Logic (PTL) circuits have been proposed that are claimed to have better performance in area, speed and power. Most current PTL logic circuits are composed of a limited number of basic PTL cells (say 2 to 5 types of cells only). However, current placement-and-routing (P&R) CAD tools are mainly designed based on CMOS cell library which usually contains many cells with different logic functions. Thus the P&R tool does not fully exploit the features of the synthesized PTL gate-level netlists. In this thesis, we present a P&R tool dedicated to the generation of the final physical layout for the PTL netlists that are generated from a PTL synthesizer. This backend tool considers the efficient placement and routing of the PTL cells in order to reduce the area cost and to reduce the impact of the interconnection wirings on speed and power performances. Besides, in this thesis, the critical paths of the PTL netlists will be identified and the corresponding input patterns to activate these critical paths will be generated for post-layout speed simulation using HSPICE or Nanosim. In summary, the layout generator in this thesis performs the P&R of PTL netlists and also automatically find the critical paths and their corresponding input patterns.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0721105-155057 |
| Date | 21 July 2005 |
| Creators | Lin, Su-ya |
| Contributors | Ko-chi Kuo, Chua-chin Wang, Shen-Fu Hsiao, Shiann-rong Kuang, Ming-Der Shieh |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721105-155057 |
| Rights | not_available, Copyright information available at source archive |
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